Common mode scan based BIST for stuck-at-fault and path delay fault
By: S, Ram Vishnu
.
Contributor(s): T. Yasodha.
Publisher: New Delhi STM Journals 2018Edition: Vol, 8(2), May-August.Description: 72-78p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
Journal of VLSI design tools & technology (JoVDTT)Summary: Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach between external testing and built-in self-test (BIST) is analyzed. The proposed method is based on weighted pseudorandom testing which uses a novel approach for compressing, and storing the weight sets. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at speed test using existing practical design-for-testability structures, such as scan design. In this work, a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The approach provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over existing methods.
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School of Engineering & Technology Archieval Section | Not for loan | 2018150 |
Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach between external testing and built-in self-test (BIST) is analyzed. The proposed method is based on weighted pseudorandom testing which uses a novel approach for compressing, and storing the weight sets. Most existing test generation tools are either inefficient in automatically identifying the longest testable paths due to the high computational complexity or do not support at speed test using existing practical design-for-testability structures, such as scan design. In this work, a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The approach provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over existing methods.
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